Already known is the phase-locked loop technique for producing a clock having a frequency twice that of the input clock.
In this technique, the frequency doubler circuit typically comprises a phase-locked loop, of PLL structure, or of DLL (Delay-Locked Loop) structure. Such structures are made up of the same blocks but arranged differently. These blocks comprise a voltage-controlled delay line (looped in a PLL structure to form a voltage-controlled oscillator), a phase comparator, a frequency divider and a low-pass filter.
Such a frequency doubler circuit is complex to design, particularly because of the stability problems for a PLL structure, occupies a large area and can produce a significant random phase offset, or jitter.
Also, the adjustment resolution of the duty cycle is not continuous, and is directly linked to the number of cells forming the delay line, said number having to increase to increase the resolution of the adjustment.
Also known is the so-called “dual-ramp or phase-shift” technique, for producing a clock having a frequency twice that of the input clock. Such a known technique generally uses an exclusive OR gate XOR receiving as input two clocks of the same frequency, offset relative to each other and delivering as output a double-frequency clock with a duty cycle dependent on the phase offset between the two input clocks.
The phase offset is typically produced using a voltage comparator which compares a ramp of voltages generated in synchronism with one of the input clocks with a reference voltage. The switchover points correspond to the edges of the offset clock.
Such a technique uses two voltage ramps, a positive one generated on the half-period of the input clock and the other negative one generated on the next half-period. Two switchovers are thus obtained using a comparator.
In such a dual-ramp system, it is difficult to perfectly control the phase offset between the two clocks, the latter depending on the difference in slope between the positive and negative ramps. It is also necessary to know the amplitude and the mean of the “triangle” of voltages generated in order to adjust the reference level for the comparison. This adds complexity, increases the surface area of the circuit and reduces the precision of the duty cycle.
U.S. Pat. No. 5,257,301 describes a frequency doubler relying on the dual-ramp technique. However, the frequency doubler in this case comprises a large number of comparators for varying the duty cycle inasmuch as one comparator is needed for each duty cycle value.
Also known is a technique based on an automatic loop system for compensating the problems of matching between the ramps. European Patent No. 0155041 describes this technique in which the double frequency clock is “averaged” in order to extract a voltage proportional to the duty cycle and reintroduce it as input to the system on the switchover threshold of the comparator. In European Patent No. 0155041, instead of a voltage ramp generation, there is a direct generation of a double-frequency clock by using an exclusive OR gate and a delay cell. The double-frequency clock obtained from the exclusive OR gate has a duty cycle dependent on the delay between the two input signals of the exclusive OR gate. This double-frequency clock is, after integration, compared to a voltage reference proportional to the duty cycle at the output of the system. Such a technique is not very compact because, on the one hand, the delay cell has to generate a significant delay and comprises in particular high-value capacitors and, on the other hand, the integrator consists of a capacitor and a resistor, both of high values.